1. Field of the Invention
This invention generally relates to finFET spacer formation.
2. Description of the Background
The term FinFET generally refers to a nonplanar, double-gate transistor. Integrated circuits that include FinFETs may be fabricated on a bulk silicon substrate or, more commonly, on a silicon-on-insulator (SOI) wafer that includes an active SOI layer of a single crystal semiconductor, such as silicon, a semiconductor substrate, and a buried insulator layer, e.g., a buried oxide layer that separates and electrically isolates the semiconductor substrate from the SOI layer. Each FinFET generally includes a narrow vertical fin body of single crystal semiconductor material with vertically-projecting sidewalls. A gate contact or electrode intersects a channel region of the fin body and is isolated electrically from the fin body by a thin gate dielectric layer. At opposite ends of the fin body are heavily-doped source/drain regions.
Conventional methods of forming the fin body utilize subtractive techniques in which a uniformly thick layer of single crystal silicon is patterned by masking and etching with a process like reactive ion etching (RIE). The width of the fin body is related to the line width of a resist mask or a hard mask. The nominal line width is specified either by photolithographic techniques or by sidewall image transfer from an overlying spacer but may be influenced by other factors. Forming the spacer around the gate is essential for finFET fabrication. However, given the three dimensional structure of the finFET, current processes for forming the finFET are difficult to employ because the spacer is undesirably formed about the source and the drain regions.
Accordingly, there is a need for fabrication processes for spacer formation in finFET structures.